Zero latency, low gate count, low power, asynchronous Reed Solomon Code based Erasure code for RAID FEC:
The whole operation of encoding and decoding is asynchronous and is pure combinatorial gates without use of any synchronous logic, making it zero latency RTL.
Symbol size is ‘m’ bits for all Galois Field operations.
The main features are:
- 1. Asynchronous operation
- 2. No clocks required.
- 3. No storage like memories SRAMS/ROMS/FilipFlops used
- 4. No iterative Feedback in the pipeline
- 5. All operation is performed in 0 clock cycles.
- 6. RTL code is generated with parameters of
- a) “m” the degree of primitive polynomial
- b) “t_max” maximum value of error symbols that can be corrected.
- c) corrects up to maximum number of erasure positions
- d) number of symbols by which the code is shortened.
- e) The number of error symbols (“t”) is programmable upto “t_max” .
- 7. Separate encoders are for every “t” .
- 8. Decoder shared for various values of “t” upto “t_max”
- 9. Lint clean code, verified for various values of “m”, “t_max”, “t” and shortened code.
- 10. Size of code differs for various values of “m”, “t_max” and number of symbols by which the code is shortened.
Every symbol and primitive polynomial used of degree ‘m’ and ‘n’ is ((1<<‘m’)-1) .Shortened ‘n_short’ is less than ‘n’ where symbols (‘n’ – ‘n_short’) are 0 . If the code has ‘t’ error correcting capability then ‘k’ = ‘n’ – 2*’t’=no. of message symbols. Here 2*’t’ erasures can be recovered.
RTL is completely configurable for ‘m’ , ‘n_short’ or ‘t’. Typically, but not necessarily ‘m’ lies between 5 to 15
ECC, number of parity symbols is 2*’t’.
Errors_correctable = floor((2*tt-no_eras)/2)
The Erasure correcting Code consists of:
- Encoder:
- A. It has programmable input data bus width. The whole encoding can be completed in 0 cycle
- Decoder:
- A. Phi Calculator: It takes in erasure locations and number of erasures and generates phi
- B. Syndrome Calculator: It can generate all syndromes in 0 clocks, or serially in as large as ‘n_short’ clocks
- C. BerlekampMasy Circuit: it generates error locator polynomial for Chien search engine
- D. Parallel Chien Search Engine: It finds error locations in as little as 0 clock or as large as ‘n_short’ clocks
- E. Forney Circuitry: It can give the symbol to correct the data at error location indicated by Chien Engine.
Applications:
1. RAID
2. Error Correction
3. DPU for DataCenters
