Hamming Code ECC

Hamming Code ECC has:

The RTL is configurable for number of message bits that need ECC protection. Once RTL is generated it is fixed.

1. RTL has no RAMS/ROMS/Flip Flops.
2. No iterative Feedback in the pipeline

It can do 1 bit error correction and 2 bit error detection.

It is a completely asynchronous design for encoder and decoder

Encoder:

•  The input is message bits which get added with ECC bits for Error Correction
• Completely asynchronous design

Decoder

• It takes in message bits and ECC bits .
• It can do 1 bit error correction and 2 bit error detection.
• completely asynchronous design
• Indicates if uncorrectable error occurred
• If 1 bit error, location searched and  data is corrected.

Applications:

SRAMS ROMs in ASIC/FPGA which require data protection against 1bit error faults for any rows in the memory

DataSheet