BCH Error Correcting Code ECC

BCH Error Correcting Code ECC

BCH code statistics for different `$mm`  `$tt`

 

Zero latency, low gate count, low power, asynchronous BCH Code based Error Correction FEC:

The whole operation of encoding and decoding is asynchronous and is pure combinatorial gates without use of any synchronous logic, making it zero latency RTL.

Symbol Size is 1 bit and variables are ‘m’ bits wide for Galois Field operations.

The main features are:

  • 1. Asynchronous operation
  • 2. No clocks required.
  • 3. No storage like memories SRAMS/ROMS/FilipFlops used
  • 4. No iterative Feedback in the pipeline
  • 5. All operation is performed in 0 clock cycles.
  • 6. RTL code is generated with parameters of
    • a) “m” the degree of primitive polynomial
    • b) “t_max” maximum value of error symbols that can be corrected.
    • c) number of symbols by which the code is shortened.
    • d) The number of error symbols (“t”) is programmable upto
      “t_max” .
  • 7. Separate encoders are for every “t” .
  • 8. Decoder  shared for various values of “t” upto “t_max”
  • 9. Lint clean code, verified for various values of “m”, “t_max”, “t” and shortened code.
  • 10. Size of code differs for various values of “m”, “t_max” and number of symbols by which the code is shortened.

Every symbol and primitive polynomial used of degree ‘m’ and ‘n’  is ((1<<‘m’)-1) .Shortened ‘n_short’ is less than ‘n’ where symbols (‘n’ – ‘n_short’) are 0 . If the code has ‘t’ error correcting capability then  ‘k’ = ‘n’ – 2*’t’ = no. of message symbols.

RTL is completely configurable for ‘m’ , ‘n_short’ or ‘t’. Typically, but not necessarily ‘m’ lies between 5 to 15

ECC, number of parity symbols is 2*’t’.

Errors_correctable  are upto ‘tt’, if more than ‘tt’ errors then indicated as uncorrectable.

The Error correcting Code consists of:

  • Encoder:
    • A. It has programmable input data bus width. The whole encoding can be completed in 0 cycle
  • Decoder:
    • A. Syndrome Calculator: It can generate all syndromes in 0 clocks, or serially in as large as ‘n_short’ clocks
    • B. BerlekampMasy Circuit: it generates error locator polynomial for Chien search engine
    • C. Parallel Chien Search Engine: It finds error locations in as little as 0 clock or as large as ‘n_short’ clocks
  1. Applications:
  2. SSD Controller
  3. Space Communications
  4. QR Code
  5. Optical Communication
  6. High Speed Communications
  7. SRAMS in chips ASICS can have memory repair using this circuit
  8. memory ECC in BIST
    1. Hamming Code will protect against 1 bit errors and detect only upto 2 bit errors
    2. BCH can correct upto `$tt` bit errors where `$tt` is decided when code is generated
    3. BCH can detect if more than `$tt` bit errors have occurred. Here symbol is 1 bit.
  9.  802.3-2008 and IEEE 802.3ba-2010 Clause 74 BCH(2112,2080)
  10.  802.3bs BCH(2880, 2570, t=25) BCH(4416, 4112, t=23

DataSheet